Broadband communication integrated circuits employ signal processing techniques to make full use of the available bandwidth and signal to noise space that exist over the transmission medium, for example an unshielded twisted pair wire for ADSL or coax cable for cable modems. When partitioning the signal processing task between analog and digital, the system architect tries to put as much of the signal processing functionality in the digital domain. The analog front-end (hereinafter “AFE”) on the receiver side is typically a high resolution analog-to-digital convertor (hereinafter “ADC”) preceded by a track-and-hold circuit (hereinafter “T/H circuit”) or sample and hold circuit (hereinafter “S/H circuit”). The AFE may also comprise a programmable gain amplifier (hereinafter “PGA”) in front to make full use of the ADC input range.
A conventional T/H circuit has two modes of operation: a track mode and a hold mode. During track mode, the T/H circuit is designed to track an analog input signal. During hold mode, the T/H circuit is designed at specified intervals to hold at its output the instantaneous value of the input signal. The T/H circuit is particularly useful as a first stage of an analog-to-digital converter. The held values of the input signal are provided as signal samples to a following stage of the ADC, which converts them to an equivalent digital signal.
S/H circuits provide a series of continuous held samples, one immediately after the other without gaps. An S/H circuit may be constructed from a pair of T/H circuits. The track mode of one track-and-hold circuit substantially coincides with the hold mode of the other circuit and the track mode of the other track-and-hold circuit substantially coincides with the hold mode of the one circuit.
The T/H or S/H circuit is often necessary to relax the ADC timing requirements. A S/H circuit samples the input signal only for a very short period of the sample clock and then provides a still signal for the ADC for almost a full clock cycle. A T/H circuit first tracks the input signal and then samples it. Usually tracking and holding takes half of a clock cycle in a T/H circuit, thus leaving less time for the ADC to do the analog to digital conversion. While the rest of the application will refer to T/H circuits, those skilled in the art will realize that the following discussions are also applicable to S/H circuits.
FIG. 1 is a block diagram of part of a prior art analog front end system 100 comprising a T/H circuit 102 and an ADC 104. In current prior art AFE systems, the output of the T/H circuit, Vtho 108, is coupled directly to the input, Vadin 112, of the ADC circuit 104. Because the load of the T/H circuit is the full input capacitance of the ADC, this capacitance must be taken into account for the stability of the T/H circuit 102. The load of the T/H circuit 102 directly determines the power required in the output stage of the T/H circuit 102. Thus, the power consumed at the output of the T/H circuit can be quite significant depending on the size of the load. Moreover, the more power that is consumed by the T/H circuit, the larger the area required by the T/H circuit 102.
FIG. 2 illustrates a conventional T/H circuit. A T/H circuit requires a switch and some memory element, usually a capacitor. A T/H circuit has two modes of operation: a “track mode” and a “hold mode”. During the hold mode, the switch in the T/H circuit is opened, and the capacitor remembers the input signal voltage that was there just before the switch opened. When the switch is opened, the output voltage of the T/H remains stable so that the ADC can start converting the output voltage of the T/H circuit into a digital code. During the track mode, the switch in the T/H circuit is closed. Due to the finite impedance charging the capacitance, a certain amount of time is required for the voltage on the capacitor to approach the input signal voltage, after which the out voltage of the T/H circuit will closely track the input signal.
Broadband communication chips use the latest silicon technologies to yield cost-effective products. In such silicon technologies, the power supply voltage is very low, thus restricting the available circuit topologies that can be used to achieve the required performance is all components in an analog front end. Thus, the absolute input voltage range for the ADC is also low. This in turn requires higher absolute accuracy from the ADC which means more area and power. In a lot of A/D architectures, this means higher input capacitance.
Another disadvantage of current prior art systems is the high power consumption at the output stage of the T/H circuit due to the inherent stability requirement of feedback amplifiers. In a feedback architecture such as the two stage amplifier/negative feedback opamp based T/H circuit, stability is important because the ADC can often have a very high input capacitance as explained above. The T/H circuit must on the one hand achieve a very high bandwidth to process the incoming signal at the required clock frequency, and on the other hand it must do that while driving a potentially high load. In order to have no ringing or overshoot, the amplifier should be designed to have about 60 degrees of phase-margin. The latter requires the non-dominant pole to be located at sufficient high frequency, about 4× the dominant pole frequency in most practical cases to achieve sufficient phase margin. This non-dominant pole is usually set by the output stage and its load. So a 4× higher bandwidth then the signal bandwidth is required in the output stage and this in the presence of a large, usually capacitative, load of the ADC.
Thus, it is desirable to provide an analog front end system comprising a T/H circuit and ADC which has low power consumption and a small area at the output stage of the T/H circuit while maintaining high speed and accuracy.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.